XC7Z035-2FFG676I - Circuitus Integrati (IC), Embedded, Systema de Chip (SoC)
Product attributa
| EXEMPLUM | DESCRIPTIO |
| Categoria | Integrated Circuitus (IC) |
| Mfr | AMD |
| Series | Zynq®-7000 |
| sarcina | Tray |
| Product Status | Active |
| Architecture | MCU, FPGA |
| Core Processor | Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ |
| Flash Size | - |
| RAM Location | 256KB |
| Peripherales | DMA |
| Connectivity | CANbus, EBI/EMI, Ethernet, I²C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
| Celeritas | 800MHz |
| Primaria attributa | Kintex™-7 FPGA, 275K Cellulae Logicae |
| Operating Temperature | -40°C ~ 100°C (TJ) |
| Sarcina / Case | 676-BBGA, FCBGA |
| Elit Fabrica Package | 676-FCBGA (27x27) |
| Numerus I / O * | 130 |
| Basis Product Number | XC7Z035 |
Documenta & Media
| RESOURCE EXEMPLUM | LINK |
| Datasheets | Zynq-7000 Omnes Programmabiles SoC Overview |
| Environmental Information | Xiliinx RoHS Cert |
| Featured Product | Omnes Programmabiles Zynq®-7000 SoC |
| PCN Design/Specification | Productum Vestigium Chg 31/Oct/2016 |
| PCN Packaging | Multae machinae 26/Jun/2017 |
| EDA exemplum | XC7Z035-2FFG676I by SnapEDA |
Environmental & Import Classifications
| TRIBUO | DESCRIPTIO |
| RoHS Status | ROHS3 Compliant |
| Humorem Sensitivity Level (MSL) | 4 (LXXII Horae) |
| SPATIUM Status | SPATIUM Unaffected |
| ECCN | 3A991D |
| HTSUS | 8542.39.0001 |
Zynq-7000 Genus Description
Familia Zynq-7000 flexibilitatem et scalam FPGA offert, dum effectum, potestatem et usum usui praebens.
typically consociata cum ASIC et ASSPs.Circumspicit machinas in Zynq-7000 familia permittit designers ad scopum
sumptus-sensitivos necnon applicationes summus perficientur ex uno suggestu utens instrumentorum industriarum vexillum.dum quisque
fabrica in Zynq-7000 familia easdem PS continet, copiae PL et I/O inter machinas variant.Quam ob rem
Zynq-7000 et Zynq-7000S SoCs amplis applicationibus inservire possunt in iis:
• Automotive auxilium coegi, informationes exactoris et infotainment
• Iaci camera
• Industriae motoris imperium, networking industrialis, visio machinalis
• IP et Smart camera
• LTE radio et baseband
• Medical diagnostica et imaginatio
Multifunction • typographos
• Video et nocturno apparatu
Architectura Zynq-7000 dat exsecutionem logicae consuetudinis in PL et in programmate consuetudinis in PS.Singularis et differentialis ratio functiones permittit ad consequendum.Integratio PS cum PL gradus perficiendi permittit quod solutiones duae chippis (exempli gratia ASSP cum FPGA) aequare non possunt ob limitata I/O latitudo, latency et potentiarum rationes.
Xilinx magnum numerum mollium IP praebet pro familia Zynq-7000.Sta-solus et Linux fabrica coegi praesto sunt periphericis in PS et in PL.Vivado® Design Suite evolutionis environment dat celeri producto progressionem pro software, hardware, ratio machinarum.Adoptio ARM dicentis PS etiam latum amplis instrumentorum partium tertiarum et IP provisoribus in compositione cum PL ecosystem Xilinx existentis affert.
Inclusio processus applicationis praebet sustentationem systematis operandi summus gradus, eg Linux.Aliae rationes normae operandi cum processus Cortex-A9 adhibitae sunt etiam pro familia Zynq-7000 prompta.PS et PL in ditionibus separatis potestates sunt, utentem harum machinorum ad PL pro administratione potentiae, si opus sit, deprimant.Processores in PS semper primo tabernus, praebens programmatum centrum accessionis pro PL configuratione.PL figuratio a programmate in CPU currit, ergo ASSP ocreae similis est.
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