(Electronic Components) 5V927PGGI8

Description:

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Product Detail

Product Tags

Product attributa

EXEMPLUM	DESCRIPTIO
Categoria	Integrated Circuitus (IC) Horologium / Timing Horologium Generantibus, PLLs, Frequentia Synthesizers
Mfr	Renesas Electronics America Inc
Series	-
sarcina	Tape & Reel (TR)
Product Status	Obsoletum
Type	Horologium Generator
PLL	Ita cum bypass
Input	LVTTL, Crystal
Output	LVTTL
Circuitus numerus	1
Ratio - Input: Output	2:4
Differentialis - Input: Output	Minime
Frequentia - Max	160MHz
Dividens/Multiplier	Ita non
Voltage - Supple	3V ~ 3.6V
Operating Temperature	-40°C ~ 85°C
Adscendens Type	Superficie montis
Sarcina / Case	16-TSSOP (0.173″, 4.40mm Latitudo)
Elit Fabrica Package	16-TSSOP
Basis Product Number	IDT5V927

Documenta & Media

RESOURCE EXEMPLUM	LINK
Datasheets	IDT5V927
PCN Obsolescene/EOL	Revision 23/Dec/2013 Multae machinis 28/Oct/2013
HTML Datasheet	IDT5V927

Environmental & Import Classifications

TRIBUO	DESCRIPTIO
Humorem Sensitivity Level (MSL)	1 (Unlimited) ;
SPATIUM Status	SPATIUM Unaffected
ECCN	EAR99
HTSUS	8542.39.0001

Additional Resources

TRIBUO	DESCRIPTIO
Alia Nomina	5V927PGGI8
Latin Package	4,000

Product Details
XXIV-DIGITAL PROCESSOR signum

Motorola DSP56307, membrum familiae DSP56300 programmalium processuum digitalium (DSPs), subsidia wireless infrastructuram applicationum cum operationibus generalibus eliquandi sustinet.Chip auctus colum coprocessor (EFCOP) processus algorithms sparguntur in parallelis cum operatione core, ita altiore DSP effectus et efficientia crescens.Sicut ceteri familiares sodales, DSP56307 summus perficientur utitur, machinam unius cycli per instructionem (codice-compatible cum Motorolas familiari populari DSP56000 core), dolium shifter, 24-bit alloquens, cella instructione ac recta memoria accessum moderatoris, ut in Figura 1. DSP56307 perficiendum praebet ad 100 milliones instructionum (MIPS) per secundam utens horologii interni 100 MHz cum 2.5 core volt et 3.3 volt input/output potestatem independentem.

Overview
Per secundam generationem ASMBL (Mutularis Clausus Pii Progressi) architecturae columnae substructae, XC5VLX330T-3FFG1738I quinque suggesta distincta continet (sub-familia), electissima quavis familia FPGA oblata.In unoquoque suggestu diversam rationum linearum rationem continet ad necessitates compellendi varietatem consiliorum logicarum progressarum.Praeter antecedens, summus perficientur logicae fabricae, XC5VLX330T-3FFG1738I FPGAs multas insunt caudices duro-IP systematis gradus, inter potentes 36-Kbit scandalum RAM/FIFOs, generationis secundae 25 x 18 DSP crustae, selectae IO technicae cum structuris. in digitally continentem impedimentum, Chip Sync-synchronum cuneos, systematis monitorem functionis;

FEATURES
Princeps euismod DSP56300 Core
● 100 decies centena instructiones per secundam (MIPS) cum 100 MHz horologium ad 2.5 V core et 3.3 VI/O
Object codice compatible cum DSP56000 core
Valde parallela disciplinam paro
Data arithmetica logica unitas (ALU)
- Plene pipelineata 24 x 24-bit
- 56-bit dolium parallelum shifter (fast trabea et ordinationem; bit amnis generationis et parsing)
- Conditionalis ALU instructions
- 24-bit vel XVI frenum arithmeticum subsidium sub software potestate
Program imperium unitas (PCU)
- Positio independens codice (PIC) firmamentum
- Modi ipsum pro DSP applicationes (including statim exsertiones)
- De-chip disciplinam cache moderatoris
- De-chip memoria-expandable hardware ACERVUS
- Nested hardware DO ansas
- Fast auto- reditus obloquitur
Dirige memoria accessum (DMA)
- Sex canales DMA accessibus internis et externis sustinendis
- One-, two-, and three dimensional translations (including circularis buffering)
- Finis-of-translatio obloquitur
- Triggering from interrupt lines and all peripherals
Phase-clausa loop (PLL)
- Permittit mutationem potentiae inferioris dividere factor (DF) sine iactura seriae
- Output horologium cum PRONUS eliminationis
Hardware debugging subsidium
- De Chip Emulationis (De CE) moduli
- Articulus test actio coetus (JTAG) test aditus portum (TAP)
- Inscriptio vestigii modus reflectitur Program accessibus internis RAM ad portum externum