5CEFA5F23I7N Cyclone® VE Field Programmable Gate Array (FPGA) IC 240 5001216 77000 484-BGA
Product attributa
| EXEMPLUM | ILLUSTRATO |
| genus | Ager Programmabilis Porta Arrays (FPGAs) |
| manufacturer | Intel |
| series | Cyclone® VE |
| wrap | lance |
| Product status | Active |
| DigiKey programmable est | Non verificatur |
| LAB/CLB numerus | 29080 |
| Numerus elementorum logicae / unitates | 77000 |
| Summa numerus RAM bits | 5001216 |
| I/O | 240 |
| Voltage - Power copia | 1.07V~1.13V |
| Genus institutionem | Superficiem tenaces genus |
| Operating Temperature | -40°C ~ 100°C(TJ) |
| Sarcina / Praesent | 484-BGA |
| Vendor component encapsulation | 484-FBGA (23x23) |
| Product dominum numerum | 5CEFA5 |
Product Introduction
Cyclone® V cogitationes ordinantur simul accommodare imminutionem potentiae consumptionis, sumptus, temporis ad mercatum requisita;et augendae band longae requisita ad altum volumen et applicationes sensitivas sumptus.Consectetur cum transceptis integris et durae memoriae moderatoris, machinae Cyclonae V aptae sunt applicationibus in mercatu industriali, wireless et wireline, militari, et autocineto.
Product Features
Technology
- TSMC's 28-nm low-power (28LP) process technology
- 1.1 V core voltage
Packaging
- Wirebond humilis-halogen fasciculis
- Multiplex fabrica densitates cum compatible sarcina vestigiorum inconsutilem migrationis inter diversas densitates fabrica
- RoHS-obsequens et plumbeus optiones
Summus perficientur FPGA fabricae
- Consectetur VIII-input ALM cum quattuor commentariis
Internus memoria caudices
- M10K-X-kilobits (Kb) memoria cuneos cum mollis erroris correctionis code (ECC)
- Logicae Memoria ordinata scandalum (MLAB) -640-bit distributum LUTRAM ubi usque ad 25% de eleemosynis uti potes memoria MLAB
Hard IP caudices embedded
- Paternum subsidium usque ad tres gradus praecisionis notabiles processus (tres 9 x 9, duo 18 x 18, vel multiplicatoris 27 x 27) in eodem clausus variabili praecisione DSP.
- LXIV frenum accumulator et Caesar
- Internum coefficiens memoria embedded
- Preadder / detractor in melius efficientiam
- DDR3, DDR2, et LPDDR2 cum 16 et 32 frenum ECC support
- PCI Express* (PCIe*) Gen2 et Gen1 (x1, x2, vel x4) durum IP cum multifunctioni auxilio, endpoint et portus radicis
Configurationis
- amper protection-comprehensive design protection to protect your valuable IP investments
- Consectetur vexillum encryption provectus (AES) features design securitatem
- CvP
- Dynamica reconfiguratio FPGA
- Activa Vide (AS) x1 et x4, Vide passivam (PS), JTAG, ac parallelam passivam passivam (FPP) x8 et x16 optiones conformationis
- Internum scrubbing (2)
- Reconfiguration partialis (3).
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